1. Field
This disclosure relates generally to contacts in a semiconductor device, and more specifically, to shared contacts in a semiconductor device.
2. Related Art
In semiconductor manufacturing, one of the most important factors for success is having good yield. Thus there is a continuous effort to make yields better in the face of continuing shrinkages in geometries which tend to increase leakage. Increases in leakage decrease yield. For a given voltage, a decrease in distance across which that voltage is supported will tend to increase leakage at that voltage. The amount of leakage for a single device may be very small but that leakage may be multiplied by a very large number. This is particularly true in a memory array. Memories are now being produced with gigabits so any leakage when multiplied by the number of memory cells can be very significant. In the case of SRAMs in particular one of the issues concerning leakage arises from an efficient manner of providing a contact in which a gate of one transistor is connected to the drain of another transistor. Many such connections exist, but for efficient layout of the SRAM cell, the gate and the drain are very close together where the connection is made. This results in using what is often called a shared contact.
Shown in FIG. 1 is a circuit diagram of a conventional SRAM cell 10 that has, among other elements, a P channel transistor with a drain 20 and a P channel transistor 14 having a gate electrode 16. A conductor 18 extends from gate electrode 16 to be connected to drain 20 with a shared contact 22. The P channels are connected symmetrically so the other P channel gate and drain are similarly connected with a shared contact. The N channels also have a similar coupling but do not generally benefit from a shared contact because the contact points are further apart, so conventional vias connected to an overlying metal layer are used.
Shown in FIG. 2 is a semiconductor structure 24 showing in cross section a portion of SRAM cell 10 prior to forming shared contact 22 showing gate electrode 18 and drain 20. As shown in FIG. 2, semiconductor device 24 also includes a substrate 26 that is N type, shallow trench isolation (STI) 28 formed of oxide in substrate 26, a silicide layer 21 on drain 20, a sidewall spacer 32 around gate electrode 18, a silicide layer 36 on gate electrode 18, an oxide liner 34 on the sidewalls of gate electrode 18 and under sidewall spacer 32, a nitride layer 46 over drain 20, silicide layer 36, sidewall spacer 32, and STI 28, and an oxide layer 48 over nitride layer 46. Oxide layer 48 is much thicker than nitride layer 46 and nitride layer 46 is much thicker than oxide liner 34. Silicide layer 21 is for having a low resistance contact with drain 20 and may be considered part of the drain of transistor 12 and is achieved by siliciding a portion of drain 20. Similarly, silicide layer 36 is achieved by siliciding gate electrode 18. As shown at the surface of STI 28 where STI 28 joins drain silicide 21, there is a divot 50 which is an area where nitride 46 extends into STI 28 below the level of the top surface of drain 20. Divot 50 arises due to the various etches that are performed in forming the transistors of SRAM cell 10 of FIG. 1. The functioning of the SRAM cell depends on the PN junction formed between drain 20 and substrate 26. The region shown as substrate 26 may be formed as a well that is formed as N type. The lowest portion of divot 50 is a distance M away from substrate 26. Semiconductor device 24 is at a stage in processing in which the transistors of SRAM cell have been formed but before they have been interconnected.
Shown in FIG. 3 is semiconductor device 24 after performing an etch that forms an opening 52 between drain 20 and silicide layer 36. An effect of this etch is that STI 28 is also etched resulting in divot 50 being lowered so that the lowest portion of divot 50 is only a distance L from substrate 26. Also sidewall spacer 32 is significantly reduced in size on the side that adjoins opening 52.
Shown in FIG. 4 is semiconductor device 24 after filling opening 52 with conductive material to form shared contact 22 that comprises a glue layer 54 and a conductive fill 56. Glue layer 54 may include a barrier layer, an adhesion layer, and a seed layer. Conductive fill 56 may include tungsten. This shows that contact fill 56 is only a distance L from substrate 26 and is much closer to gate electrode 18. These reduced distances tend to increase leakage. As distance L becomes smaller, the leakage increases significantly and if it reaches below the interface between drain 20 and substrate 26, the bit will fail due to bypassing the PN junction between substrate 26 and drain 20. The distance L is difficult to control precisely so this type of direct and immediate failure can occur. Also any leakage at this point degrades performance of the bit cell and can result in data retention failures.
Thus, there is a need to reduce the failures in a shared contact such as induced by the described process and resulting structure shown in FIG. 4.